Publication (International Journals –
SCI/SCIE)
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37. Seokwon Choi, Changmin Song, and Young-Chan Jang, ¡°A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver
with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor,¡± MDPI Sensors, vol. 21, no. 15, pp. 5197,
Jul. 2021. 36. Jisu Son and Young-Chan Jang, ¡°A
10-bit 10-MS/s Asynchronous SAR ADC with Input Offset Calibration using
Capacitor DAC,¡± IEIE Journal of
Semiconductor Technology and Science, vol. 20, no. 6, pp. 518-525, Dec.
2020. 35. Pil-Ho Lee and Young-Chan Jang, ¡°A
6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent
Equalization,¡± IEEE Transactions on
Circuits and Systems II: Express Briefs, vol. 67, no. 11, pp. 2672-2676,
Nov. 2020. 34. Seokwon Choi, Pil-Ho Lee, Jin-Wook Han,
Sang-Dong Kim, and Young-Chan Jang,
¡°A MIPI Receiver Bridge Chip
supporting 5-Gb/s/lane D-PHY and 3-Gsymbol/s/lane C-PHY,¡± IEIE Journal of Semiconductor Technology
and Science, vol. 20, no. 1, pp. 29-40, Feb. 2020. 33. Jisu Son and Young-Chan Jang, ¡°A
10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting
common-mode voltage and controlling input voltage range,¡± IEICE Electronics Express, vol. 16,
no. 22, pp. 1-5, Nov. 2019. 32. Pil-Ho Lee and Young-Chan Jang, ¡°A
20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY
Interface,¡± IEEE Transactions on
Consumer Electronics, vol. 65, no. 4, pp. 484-492, Sep. 2019. 31. Han-Yeol Lee, Eunji Youn, and Young-Chan Jang, ¡°A 10-bit 100-MS/s Pipelined SAR ADC with
Redundancy Generation using Capacitor-based DAC and Linearity-improved
Dynamic Amplifier,¡± IEIE Journal of
Semiconductor Technology and Science, vol. 19, no. 4, pp. 378-387, Aug.
2019. 30. Pil-Ho Lee and Young-Chan Jang, ¡°A
3 Gbps/lane MIPI D-PHY Transmission Buffer Chip,¡± IEICE Transaction on Fundamentals, vol. E102-A, no. 6, pp.
783-787, Jun. 2019. 29. Ho-Seong Kim, Pil-Ho Lee, Jin-Wook Han,
Seung-Hun Shin, Seung-Wuk Baek, Doo-Ill Park, Yongkyu Seo, and Young-Chan Jang, ¡°A 10 Gbps D-PHY Transmitter Bridge Chip
for FPGA-based Frame Generator supporting MIPI DSI of Mobile Display,¡± IEICE Transaction on Electronics,
vol. E100-C, no. 11, pp. 1035-1038, Nov. 2017. 28. Pil-Ho Lee, Han-Yeol Lee, Yeong-Woong
Kim, Han-Young Hong, and Young-Chan
Jang, ¡°A 10-Gbps Receiver Bridge
Chip with Deserializer for FPGA-based Frame Grabber supporting MIPI CSI-2,¡±
IEEE Transactions on Consumer
Electronics, vol. 63, no. 3, pp. 209-215, Aug. 2017. 27. Pil-Ho Lee, Han-Yeol Lee, Hyun-Bae Lee,
and Young-Chan Jang, ¡°An On-Chip Monitoring Circuit for Signal-
Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces with Source-Synchronous
Clock,¡± IEEE Transactions on Very
Large Scale Integration, vol. 25, no. 4, pp. 1386-1398, Apr. 2017. 26. Sang-Min Park, Yeon-Ho Jeong, Yu-Jeong
Hwang, Pil-Ho Lee, Yeong-Woong Kim, Jisu Son, Han-Yeol Lee, and Young-Chan Jang, ¡°A 10-bit 20-MS/s Asynchronous SAR ADC
with Meta-stability Detector using Replica Comparators,¡± IEICE Transaction on Electronics, vol.
E99-C, no. 6, pp. 651-654, Jun. 2016. 25. Pil-Ho Lee, Yu-Jeong Hwang, Han-Yeol Lee,
Hyun-Bae Lee, and Young-Chan Jang,
¡°An On-Chip Monitoring Circuit with
51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended
Signaling Integrity Analysis,¡± IEICE
Transaction on Electronics, vol. E99-C, no. 4, pp. 440-443, Apr. 2016. 24. Han-Yeol Lee, Dong-Gil Jeong, Yu-Jeong
Hwang, Hyun-Bae Lee, and Young-Chan
Jang, ¡°A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain
Comparator,¡± IEIE Journal of
Semiconductor Technology and Science, vol. 15, no. 6, pp. 695-702, Dec.
2015. 23. Kwang-Hun Lee and Young-Chan Jang, ¡°A
2-Gb/s CMOS SLVS Transmitter with Asymmetric Impedance Calibration for Mobile
Interfaces,¡± IEICE Transaction on
Electronics, vol. E97-C, no. 8, pp. 837-840, Aug. 2014. 22. Mungyu Kim, Hoon-Ju Chung, and Young-Chan Jang, ¡°A 10-bit CMOS Digital-to-Analog Converter
with compact size for Display Applications,¡± IEICE Transaction on Electronics, vol. E97-C, no. 6, pp. 519-525,
Jun. 2014. 21. Pil-Ho Lee, Hyun Bae Lee, and Young-Chan Jang, ¡°A 125 MHz 64-Phase Delay-Locked Loop with
Coarse-Locking Circuit independent of Duty Cycle,¡± IEICE Transaction on Electronics, vol. E97-C, no. 5, pp. 463-467,
May 2014. 20. Ji-Hun Eo, Yeon-Ho Jeong, and Young-Chan Jang, ¡°An 8-bit 100-kS/s CMOS Single-ended SA
ADC for 8 ¡¿ 8 Point EEG/MEG Acquisition System,¡± IEICE Transaction on Fundamentals, vol. E96-A, no. 2, pp.
453-458, Feb. 2013. |
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19. Han-Yeol Lee and Young-Chan Jang, ¡°A
True Single-Phase Clocked Flip-Flop with Leakage Current Compensation,¡± IEICE Electronics Express, vol. 9, no.
23, pp. 1807-1812, Dec. 2012. |
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18. Hyun Bae Lee and Young-Chan Jang, ¡°Mirrored
Serpentine Microstrip Lines for Reduction of Far-End Crosstalk,¡± IEICE Transaction on Electronics, vol.
E95-C, no. 6, pp. 1086-1088, Jun. 2012. |
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17. Ji-Hun Eo, Sang-Hun Kim, and Young-Chan Jang, ¡°A 1V 200 kS/s 10-bit Successive
Approximation ADC for a Sensor Interface,¡± IEICE Transaction on Electronics, vol. E94-C, no. 11, pp.
1798-1801, Nov. 2011. |
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16. Sang-hun Kim, Yong-Hwan Lee, Hoon-Ju Chung,
and Young-Chan Jang, ¡°A Bootstrapped Analog Switch with
Constant On-Resistance,¡± IEICE
Transaction on Electronics, vol. E94-C, no. 6, pp. 1069-1071, Jun. 2011. |
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15. Young-Chan
Jang, ¡°A Self-Calibrating
Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in
Parallel Interface,¡± IEICE
Transaction on Fundamentals, vol. E94-A, no. 2, pp. 633-638, Feb. 2011. |
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14. Young-Chan
Jang, ¡°An Unmatched Source
Synchronous I/O Link for Jitter Reduction in a Multi-phase Clock System,¡±
IEICE Electronics Express, vol. 7,
no. 11, pp. 797-803, Jun. 2010. |
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13. Young-Chan
Jang, ¡°A Swing Level
Controlled Transmitter for Single-Ended Signaling with Center-Tapped
Termination,¡± IEICE Transaction on
Electronics, vol. E93-C, no. 6, pp. 861-863, Jun. 2010. |
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12. Young-Chan
Jang, ¡°A Digital Phase
Corrector with a Duty Cycle Detector and Transmitter for a Quad Data Rate I/O
Scheme,¡± IEICE Electronics Express,
vol. 7, no. 3, pp. 146-152, Feb. 2010. |
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11. Young-Chan
Jang, Hoeju Chung, Youngdon Choi, Hwanwook Park, Jaekwan Kim, Soouk
Lim, Jung Sunwoo, Moon-Sook Park, Hyung-Seuk Kim, Sang-Yun Kim, Yun-Sang Lee,
Woo-Seop Kim, Jung-Bae Lee, Jeihwan Yoo, and Changhyun Kim, ¡°BER Measurement of a 5.8-Gb/s/pin
Unidirectional Differential I/O for DRAM Application with DIMM Channel,¡± IEEE Journal of Solid State Circuits,
vol. 44, no. 11, pp. 2987-2998, Nov. 2009. |
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10. Young-Chan
Jang, Jun-Hyun Bae, Ho-Young Lee, Yong-Sang You, Jae-Whui Kim,
Jae-Yoon Sim, and Hong-June Park, ¡°A
1.2V 7-bit 1GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration,¡±
IEEK Journal of Semiconductor
Technology and Science, vol.8, no.4, pp. 318-325, Dec. 2008. |
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9. Young-Chan
Jang, ¡°A Cascaded voting
process for Flash ADC with interpolating scheme,¡± Electronics Letters, vol. 44, no. 18, Aug. 2008. |
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8. Hyun Chul Kang, Woo-Seop Kim, Jae-Wook
Lee, Young-Chan Jang,
Hwan-Wook Park, Jonghoon Kim, Jung-Bae Lee, and Chang-Hyun Kim, ¡±BER Simulator Development for Link
Compliance Analysis,¡° IEEK Journal
of Semiconductor Technology and Science, vol.8, no.2, pp. 150-155, Jun.
2008. |
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7. Young-Chan
Jang, Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, and Hong-June Park,
¡°An 8.8-GS/s 6-bit CMOS
Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock
Generator,¡± IEICE Transaction on
Electronics, vol. E90-C, no. 6, pp. 1156-1164, Jun. 2007. |
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6. Kyu-hyoun Kim, Hoe-Ju Chung, Woo-Seop Kim,
Moonsook Park, Young-Chan Jang,
Jin-Young Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo Sun Choi, and
Changhyun Kim, ¡°An 8 Gb/s/pin 9.6 ns
Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme,¡±
IEEE Journal of Solid State Circuits,
vol. 42, no. 1, pp. 193-200, Jan. 2007. |
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5. Young-Chan Jang, Jun-Hyun
Bea, and Hong-June park, ¡°A Digital
CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control,¡± IEEE Transactions on Circuits and Systems
II: Express Briefs, vol. 53, no. 10, pp. 1063-1067, Oct. 2006. |
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4. Young-Chan Jang, Sang-Hune
Park, Seung-Chan Heo, and Hong-June Park, ¡°An 8-GS/s 4-bit 340mW CMOS Time Interleaved Flash Analog-to-Digital
Converter,¡± IEICE Transaction on
Fundamentals, vol. E87-A, no. 2, pp. 350-356, Feb. 2004. |
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3. Young-Chan Jang, Seung-Jun
Bae, and Hong-June Park, ¡°CMOS Digital
Duty Cycle Correction Circuit for Multi-Phase Clock,¡± Electronics Letters, vol. 39, no. 19,
pp. 1383-1384, Sep. 2003. |
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2. Seung-Chan Heo, Young-Chan Jang,
Sang-Hune Park, and Hong-June Park, ¡°An
8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter,¡± IEICE Transaction on Electronics, vol.
E86-C, no. 4 pp. 676-681, Apr. 2003. |
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1. Jin-Cheon Kim, Young-Chan Jang,
and Hong-June Park, ¡°CMOS
sense-amplifier based flip-flop with two N-C2MOS output latches,¡±
Electronics Letters, vol. 36, no.
6, pp. 498-500, Mar. 2000. |